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Trainee VLSI Design Engineer
We are hiring Fresh Engineers for VLSI Design & Verification role. Job location is Nashik, Maharashtra.
Job Details:
Engineer hired into this program will get trained on Digital Logic design, Design Verification methodologies, Design for testability and FPGA Emulation. After successfully completion of training you will get opportunity to work with our IP and hardware Product development teams.
Minimum Qualifications:
• Bachelors in Electronics/ Computer Engineering
3+ months of experience in the following:
• Programming experience in HDL (Verilog/VHDL/System verilog) and/or C++
Preferred Qualifications:
• Programming experience: Perl, Python and/ or TCL
• Experience with FPGAs
• Digital Logic
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E-mail your resume to hr@logicscalar.com
Digital Logic Design Engineer
Job Details:
This is a full-time role for a Digital Logic Design Engineer at Logic Scalar Technologies. The engineer will be responsible for tasks related to logic design, circuit design, physical design, computer architecture, and RTL coding. They will work on designing, implementing, and testing digital circuits and systems as part of semiconductor design projects.
Qualifications:
- 2+ years of hands-on experience
- Logic Design and Circuit Design skills
- RTL Coding proficiency
- Experience in designing and testing digital circuits
- Strong problem-solving and analytical skills
- Ability to work independently and remotely
- Bachelor's degree in Electronics Engineering, Computer Engineering, or related field
- Experience with FPGA design and verification is a plus
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E-mail your resume to hr@logicscalar.com
Design Verification Engineer
Job Details:
Performs functional logic verification of an integrated SubSystem to ensure design will meet specifications.
Defines and develops scalable and reusable block, subsystem verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications.
Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment.
Finds and implements corrective measures to resolve failing tests.
Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features.
Documents test plans and drives technical reviews of plans and proofs with design and architecture teams.
Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage.
Maintains and improves existing functional verification infrastructure and methodology.
Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products.
Candidate should be self-driven and good with digital logic fundamentals.
Qualifications
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
Bachelor's degree in Electronics Engineering, Computer science or related field.
Minimum 6 months of experience in Verilog, System Verilog or UVM methodology.
Minimum 3 months of experience in Perl or Python scripting
Preferred Qualifications:
Experience with VCS or cadence simulators
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E-mail your resume to hr@logicscalar.com
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